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@lcamtuf @gsuberland Eric says "Note that Intel's documentation says that CPUs before Ice Lake behave as if
DOITM is always set" https://lore.kernel.org/lkml/Yw0Ah5m%2F2HDDvCjS@gmail.com/
@ciphergoth @lcamtuf I read through the whole documentation page including all of the CPUID enumeration and MSR stuff, and the only detail I could find about a case that seems to *maybe* behave differently in Ice Lake compared to prior cores is that a few of the masked vector instructions that AMD implemented and Intel later ported may have variable latency depending on the contents of the mask register. It's also implied that these instructions are new to Ice Lake.
@ciphergoth @lcamtuf right, but that doesn't mean that there were any instruction timing behaviour changes in Ice Lake.
as best I can tell, this is basically Intel saying "we're going to give you a mode where all the side channel stuff is gone, and you can use that when your threat model demands it, and then we're going to compete on performance by cranking our prefetching and speculation to 11"